Network-on-Chip Architecture, TSNoC
The NEMA-GPU series is powered by an adaptive ultra low power, network-on-chip architecture (TSNoC) explicitly optimized for the memory traffic and memory patterns of NEMA GPUs.
TSNoC efficiently handles
Incoming AXI transactions semantics are transformed in the network interfaces to a packetized flow-control protocol used inside the TSNoC for fast data delivery and QoS switching. The TSNoC-internal, proprietary protocol satisfies in an adaptive manner the bandwidth and latency requirements of NEMA applications and allows our GPUs to scale to an arbitrary number of cores. The TSNoC internal protocol is the key success of NEMA interconnection because it offers an effective mean to handle and optimize the different volume and types of memory requests generated by our multicore GPU (geometry, z- and texture data etc.) in a seamless fashion.
TSNoC is fully configurable at design time including multiple customization features:
The tightly-coupled integration of NEMA cores with TSNoC simplifies the integration of our IP at system level and eases the design/verification stage. At the physical level, chip-level integration is oblivious of the potential routing congestion in a NEMA-based graphics subsystem since local routing congestion is efficiently addressed by the TSNoC in a scalable manner.